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[/] [openmsp430/] [trunk/] [core/] - Rev 169

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154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4233d 16h /openmsp430/trunk/core/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4318d 14h /openmsp430/trunk/core/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4321d 16h /openmsp430/trunk/core/
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4371d 16h /openmsp430/trunk/core/
142 Beautify the linker script examples. olivier.girard 4392d 16h /openmsp430/trunk/core/
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4396d 15h /openmsp430/trunk/core/
139 Add some SVN ignore patterns olivier.girard 4409d 01h /openmsp430/trunk/core/
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4409d 01h /openmsp430/trunk/core/
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4440d 16h /openmsp430/trunk/core/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4453d 16h /openmsp430/trunk/core/
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4461d 15h /openmsp430/trunk/core/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4537d 15h /openmsp430/trunk/core/
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4609d 16h /openmsp430/trunk/core/
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4713d 17h /openmsp430/trunk/core/
115 Add linker script example. olivier.girard 4738d 17h /openmsp430/trunk/core/
112 Modified comment. olivier.girard 4746d 16h /openmsp430/trunk/core/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4747d 16h /openmsp430/trunk/core/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4803d 15h /openmsp430/trunk/core/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4818d 15h /openmsp430/trunk/core/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4823d 22h /openmsp430/trunk/core/

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