URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [registers.v] - Rev 76

Rev	Log message	Author	Age	Path
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4933d 08h	/openmsp430/trunk/core/bench/verilog/registers.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5257d 11h	/openmsp430/trunk/core/bench/verilog/registers.v
17	Updated header with SVN info	olivier.girard	5404d 08h	/openmsp430/trunk/core/bench/verilog/registers.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5439d 08h	/openmsp430/trunk/core/bench/verilog/registers.v