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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [timescale.v] - Rev 103

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103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 4834d 21h /openmsp430/trunk/core/bench/verilog/timescale.v

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