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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg_hwbrk.v] - Rev 106

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106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4794d 19h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4815d 03h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
57 Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation.
Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.		 olivier.girard 5211d 18h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5245d 22h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_hwbrk.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5245d 23h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5367d 01h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
17 Updated header with SVN info olivier.girard 5392d 20h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5427d 20h /openmsp430/trunk/core/rtl/verilog/dbg_hwbrk.v

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