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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_dbg_uart.v] - Rev 103

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103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4822d 11h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
85 Diverse RTL cosmetic updates. olivier.girard 4858d 04h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5011d 06h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5253d 06h /openmsp430/trunk/core/rtl/verilog/omsp_dbg_uart.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5253d 07h /openmsp430/trunk/core/rtl/verilog/dbg_uart.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5374d 09h /openmsp430/trunk/core/rtl/verilog/dbg_uart.v
17 Updated header with SVN info olivier.girard 5400d 04h /openmsp430/trunk/core/rtl/verilog/dbg_uart.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5435d 04h /openmsp430/trunk/core/rtl/verilog/dbg_uart.v

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