Rev |
Log message |
Author |
Age |
Path |
192 |
Number of supported IRQs is now configurable to 14 (default), 30 or 62. |
olivier.girard |
3798d 09h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
134 |
Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability. |
olivier.girard |
4433d 09h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
117 |
To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. |
olivier.girard |
4706d 10h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
111 |
Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly. |
olivier.girard |
4740d 09h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
106 |
Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution). |
olivier.girard |
4796d 07h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
105 |
Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way. |
olivier.girard |
4811d 08h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
103 |
Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL. |
olivier.girard |
4816d 15h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
91 |
Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface. |
olivier.girard |
4829d 10h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
85 |
Diverse RTL cosmetic updates. |
olivier.girard |
4852d 08h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
60 |
Cleanup of the PC (R0) generation logic.
Formal equivalence was shown between the new and old code with Synopsys' Formality (to make sure that nothing has been broken :-P ). |
olivier.girard |
5211d 08h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
53 |
Fixed the following combinatorial timing loop:
1- irq_detect (omsp_frontend)
2- decode (omsp_frontend)
3- dbg_swbrk (omsp_dbg)
4- halt_flag_set (omsp_dbg)
6- dbg_halt_cmd (omsp_dbg)
7- irq_detect (omsp_frontend)
Without this fix, problem could occur whenever an IRQ request arrives during a software breakpoint instruction fetch. |
olivier.girard |
5218d 11h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
34 |
To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. |
olivier.girard |
5247d 10h |
/openmsp430/trunk/core/rtl/verilog/omsp_frontend.v |
33 |
In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).
In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created. |
olivier.girard |
5247d 11h |
/openmsp430/trunk/core/rtl/verilog/frontend.v |
23 |
Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct). |
olivier.girard |
5368d 13h |
/openmsp430/trunk/core/rtl/verilog/frontend.v |
17 |
Updated header with SVN info |
olivier.girard |
5394d 08h |
/openmsp430/trunk/core/rtl/verilog/frontend.v |
2 |
Upload complete openMSP430 project to the SVN repository |
olivier.girard |
5429d 08h |
/openmsp430/trunk/core/rtl/verilog/frontend.v |