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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [omsp_watchdog.v] - Rev 106

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Rev	Log message	Author	Age	Path
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4794d 06h	/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4814d 14h	/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4855d 08h	/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
34	To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix.	olivier.girard	5245d 09h	/openmsp430/trunk/core/rtl/verilog/omsp_watchdog.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5245d 10h	/openmsp430/trunk/core/rtl/verilog/watchdog.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5366d 12h	/openmsp430/trunk/core/rtl/verilog/watchdog.v
17	Updated header with SVN info	olivier.girard	5392d 07h	/openmsp430/trunk/core/rtl/verilog/watchdog.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5427d 07h	/openmsp430/trunk/core/rtl/verilog/watchdog.v

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