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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [openMSP430_defines.v] - Rev 67

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Rev	Log message	Author	Age	Path
67	Added 16x16 Hardware Multiplier.	olivier.girard	5185d 13h	/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
57	Update design to exclude the range mode from the debug hardware breakpoint units. As this feature is not used by GDB, it has been disabled in order to improve the timings and save a bit of area/utilisation. Note that if required, this feature can be re-enabled through the `HWBRK_RANGE define located in the "openMSP430_defines.v" file.	olivier.girard	5219d 02h	/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5253d 07h	/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
23	Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file. In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).	olivier.girard	5374d 09h	/openmsp430/trunk/core/rtl/verilog/openMSP430_defines.v
17	Updated header with SVN info	olivier.girard	5400d 04h	/openmsp430/trunk/core/rtl/verilog/openMSP430.inc
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5435d 04h	/openmsp430/trunk/core/rtl/verilog/openMSP430.inc

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