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[/] [openmsp430/] [trunk/] [core/] [rtl/] [verilog/] [periph/] [template_periph_8b.v] - Rev 106

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106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4794d 20h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4815d 03h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
85 Diverse RTL cosmetic updates. olivier.girard 4850d 21h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
66 The peripheral templates are now under BSD license.
Developers of new peripherals based on these templates won't have to disclose their code.		 olivier.girard 5178d 10h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5245d 23h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5367d 01h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
17 Updated header with SVN info olivier.girard 5392d 20h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5427d 20h /openmsp430/trunk/core/rtl/verilog/periph/template_periph_8b.v

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