OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] - Rev 99

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
99 Small fix for CVER simulator support. olivier.girard 4827d 05h /openmsp430/trunk/core/sim/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4827d 05h /openmsp430/trunk/core/sim/
95 Update some test patterns for the additional simulator supports. olivier.girard 4831d 05h /openmsp430/trunk/core/sim/
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 4831d 05h /openmsp430/trunk/core/sim/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4835d 06h /openmsp430/trunk/core/sim/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4858d 03h /openmsp430/trunk/core/sim/
85 Diverse RTL cosmetic updates. olivier.girard 4858d 04h /openmsp430/trunk/core/sim/
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4912d 12h /openmsp430/trunk/core/sim/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4924d 06h /openmsp430/trunk/core/sim/
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4929d 04h /openmsp430/trunk/core/sim/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5011d 06h /openmsp430/trunk/core/sim/
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5036d 06h /openmsp430/trunk/core/sim/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5038d 07h /openmsp430/trunk/core/sim/
67 Added 16x16 Hardware Multiplier. olivier.girard 5185d 13h /openmsp430/trunk/core/sim/
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5196d 04h /openmsp430/trunk/core/sim/
58 Update the debug hardware breakpoint verification patterns to reflect the latest design updates. olivier.girard 5219d 02h /openmsp430/trunk/core/sim/
55 Add a "sandbox" test pattern to play around with the simulation :-P olivier.girard 5224d 04h /openmsp430/trunk/core/sim/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5224d 07h /openmsp430/trunk/core/sim/
37 olivier.girard 5253d 05h /openmsp430/trunk/core/sim/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5253d 06h /openmsp430/trunk/core/sim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.