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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 211

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Rev Log message Author Age Path
115 Add linker script example. olivier.girard 4724d 06h /openmsp430/trunk/core/sim/rtl_sim/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4733d 05h /openmsp430/trunk/core/sim/rtl_sim/
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4789d 03h /openmsp430/trunk/core/sim/rtl_sim/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4804d 04h /openmsp430/trunk/core/sim/rtl_sim/
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4809d 11h /openmsp430/trunk/core/sim/rtl_sim/
102 Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ).
The following PUSH instructions are now working as expected:

- indexed mode: PUSH x(R1)
- indirect register mode: PUSH @R1
- indirect autoincrement: PUSH @R1+		 olivier.girard 4810d 03h /openmsp430/trunk/core/sim/rtl_sim/
101 Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source. olivier.girard 4810d 05h /openmsp430/trunk/core/sim/rtl_sim/
99 Small fix for CVER simulator support. olivier.girard 4814d 05h /openmsp430/trunk/core/sim/rtl_sim/
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4814d 05h /openmsp430/trunk/core/sim/rtl_sim/
95 Update some test patterns for the additional simulator supports. olivier.girard 4818d 05h /openmsp430/trunk/core/sim/rtl_sim/

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