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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] - Rev 54

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54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5237d 08h /openmsp430/trunk/core/sim/rtl_sim/
37 olivier.girard 5266d 05h /openmsp430/trunk/core/sim/rtl_sim/
34 To avoid potential conflicts with other Verilog modules in bigger projects, the openMSP430 sub-modules have all been renamed with the "omsp_" prefix. olivier.girard 5266d 07h /openmsp430/trunk/core/sim/rtl_sim/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5266d 08h /openmsp430/trunk/core/sim/rtl_sim/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5387d 09h /openmsp430/trunk/core/sim/rtl_sim/
19 added SVN property for keywords olivier.girard 5413d 04h /openmsp430/trunk/core/sim/rtl_sim/
18 Updated headers with SVN info olivier.girard 5413d 04h /openmsp430/trunk/core/sim/rtl_sim/
17 Updated header with SVN info olivier.girard 5413d 05h /openmsp430/trunk/core/sim/rtl_sim/
6 Some more SVN ignore properties... olivier.girard 5435d 06h /openmsp430/trunk/core/sim/rtl_sim/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5448d 04h /openmsp430/trunk/core/sim/rtl_sim/

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