OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [msp430sim_c] - Rev 207

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
207 Simulation now works seamlessly under Linux, OS-X and Windows (Cygwin) olivier.girard 3112d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
202 Add DMA interface support + LINT cleanup olivier.girard 3223d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3383d 23h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3784d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4296d 23h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4375d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4387d 10h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4588d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 4807d 01h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
76 Add possibility to simulate C code within the "core" environment. olivier.girard 4909d 00h /openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.