URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [msp430sim_c] - Rev 202

Rev	Log message	Author	Age	Path
202	Add DMA interface support + LINT cleanup	olivier.girard	3243d 12h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
200	Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains.	olivier.girard	3404d 11h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
192	Number of supported IRQs is now configurable to 14 (default), 30 or 62.	olivier.girard	3804d 13h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
151	Add possibility to configure custom Program, Data and Peripheral memory sizes.	olivier.girard	4317d 11h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
141	Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later)	olivier.girard	4395d 12h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
138	Update simulation scripts to support Cygwin out of the box for Windows users.	olivier.girard	4407d 22h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
122	Add coverage report generation (NCVERILOG only) Add support for the ISIM Xilinx simulator.	olivier.girard	4608d 13h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4827d 13h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4929d 12h	/openmsp430/trunk/core/sim/rtl_sim/bin/msp430sim_c