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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [clock_module.v] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3232d 01h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4088d 01h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4428d 02h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4735d 02h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4791d 00h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
19 added SVN property for keywords olivier.girard 5389d 00h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
18 Updated headers with SVN info olivier.girard 5389d 00h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5424d 01h /openmsp430/trunk/core/sim/rtl_sim/src/clock_module.v

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