URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_mem.s43] - Rev 200

Rev	Log message	Author	Age	Path
200	Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains.	olivier.girard	3393d 16h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43
154	The serial debug interface now supports the I2C protocol (in addition to the UART)	olivier.girard	4221d 17h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.s43
141	Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later)	olivier.girard	4384d 17h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4735d 18h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43
19	added SVN property for keywords	olivier.girard	5389d 16h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43
18	Updated headers with SVN info	olivier.girard	5389d 16h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5424d 17h	/openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.s43