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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [dbg_uart_mem.v] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3231d 21h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3392d 20h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4220d 21h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_uart_mem.v
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4305d 19h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4734d 21h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4790d 20h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4846d 19h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
19 added SVN property for keywords olivier.girard 5388d 20h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
18 Updated headers with SVN info olivier.girard 5388d 20h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5423d 20h /openmsp430/trunk/core/sim/rtl_sim/src/dbg_mem.v

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