OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.v] - Rev 202

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
202 Add DMA interface support + LINT cleanup olivier.girard 3232d 03h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
180 Add new ASIC_CLOCKING configuration option to allow ASIC implementations with FPGA clocking scheme.
Thanks to Sebastien Van Cauwenberghe's contribution :-)		 olivier.girard 4088d 03h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4428d 04h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4735d 04h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
95 Update some test patterns for the additional simulator supports. olivier.girard 4820d 04h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 4913d 05h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
19 added SVN property for keywords olivier.girard 5389d 02h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
18 Updated headers with SVN info olivier.girard 5389d 02h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5424d 03h /openmsp430/trunk/core/sim/rtl_sim/src/op_modes.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.