URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.v] - Rev 192

Rev	Log message	Author	Age	Path
192	Number of supported IRQs is now configurable to 14 (default), 30 or 62.	olivier.girard	3791d 21h	/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4426d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4733d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
95	Update some test patterns for the additional simulator supports.	olivier.girard	4818d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
19	added SVN property for keywords	olivier.girard	5387d 19h	/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
18	Updated headers with SVN info	olivier.girard	5387d 19h	/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v
2	Upload complete openMSP430 project to the SVN repository	olivier.girard	5422d 20h	/openmsp430/trunk/core/sim/rtl_sim/src/sing-op_reti.v