URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src-c/] - Rev 134

Rev	Log message	Author	Age	Path
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4439d 10h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4746d 10h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4912d 17h	/openmsp430/trunk/core/sim/rtl_sim/src-c/
76	Add possibility to simulate C code within the "core" environment.	olivier.girard	4929d 10h	/openmsp430/trunk/core/sim/rtl_sim/src-c/