URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] - Rev 200

Rev	Log message	Author	Age	Path
200	Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains.	olivier.girard	3383d 21h	/openmsp430/trunk/core/synthesis/xilinx/
134	Add full ASIC support (low-power modes, DFT, ...). Improved serial debug interface reliability.	olivier.girard	4418d 22h	/openmsp430/trunk/core/synthesis/xilinx/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4725d 22h	/openmsp430/trunk/core/synthesis/xilinx/
68	Update synthesis scripts with the hardware multiplier support.	olivier.girard	5165d 07h	/openmsp430/trunk/core/synthesis/xilinx/
62	Add Xilinx synthesis environment for size&speed analysis.	olivier.girard	5186d 09h	/openmsp430/trunk/core/synthesis/xilinx/