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[/] [openmsp430/] [trunk/] [fpga/] - Rev 106

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Rev	Log message	Author	Age	Path
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4802d 03h	/openmsp430/trunk/fpga/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4817d 03h	/openmsp430/trunk/fpga/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4821d 05h	/openmsp430/trunk/fpga/
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	4826d 03h	/openmsp430/trunk/fpga/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4827d 04h	/openmsp430/trunk/fpga/
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	4828d 04h	/openmsp430/trunk/fpga/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4831d 04h	/openmsp430/trunk/fpga/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4835d 05h	/openmsp430/trunk/fpga/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4858d 02h	/openmsp430/trunk/fpga/
85	Diverse RTL cosmetic updates.	olivier.girard	4858d 04h	/openmsp430/trunk/fpga/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4863d 05h	/openmsp430/trunk/fpga/
83	Add Oscilloscope screenshot + link to the original game.	olivier.girard	4909d 05h	/openmsp430/trunk/fpga/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4909d 05h	/openmsp430/trunk/fpga/
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4912d 03h	/openmsp430/trunk/fpga/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4912d 11h	/openmsp430/trunk/fpga/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4924d 05h	/openmsp430/trunk/fpga/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5011d 05h	/openmsp430/trunk/fpga/
73	Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh". This will prevent compatibility problems in systems where bash isn't the default shell.	olivier.girard	5036d 05h	/openmsp430/trunk/fpga/
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5038d 06h	/openmsp430/trunk/fpga/
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5185d 04h	/openmsp430/trunk/fpga/

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[/] [openmsp430/] [trunk/] [fpga/] - Rev 106

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