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[/] [openmsp430/] [trunk/] [fpga/] - Rev 110

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Rev	Log message	Author	Age	Path
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4802d 06h	/openmsp430/trunk/fpga/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4803d 20h	/openmsp430/trunk/fpga/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4803d 20h	/openmsp430/trunk/fpga/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4803d 20h	/openmsp430/trunk/fpga/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4818d 21h	/openmsp430/trunk/fpga/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4822d 22h	/openmsp430/trunk/fpga/
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	4827d 21h	/openmsp430/trunk/fpga/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4828d 22h	/openmsp430/trunk/fpga/
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	4829d 22h	/openmsp430/trunk/fpga/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4832d 22h	/openmsp430/trunk/fpga/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4836d 23h	/openmsp430/trunk/fpga/
86	Update serial debug interface test patterns to make them work with all program memory configurations.	olivier.girard	4859d 19h	/openmsp430/trunk/fpga/
85	Diverse RTL cosmetic updates.	olivier.girard	4859d 21h	/openmsp430/trunk/fpga/
84	Update SRAM model in the core testbench to prevent the IEEE warning when running simulations. Update watchdog to fix NMI synchronisation problem. Add synchronizers for the PUC signal in the debug interface.	olivier.girard	4864d 22h	/openmsp430/trunk/fpga/
83	Add Oscilloscope screenshot + link to the original game.	olivier.girard	4910d 22h	/openmsp430/trunk/fpga/
82	Update Actel example project: - synthesis scripts. - Spacewar demo program. - SVN ignore patterns for diverse directories	olivier.girard	4910d 22h	/openmsp430/trunk/fpga/
81	Initial synthesis, P&R setup for the Actel example project.	olivier.girard	4913d 20h	/openmsp430/trunk/fpga/
80	Create initial version of the Actel FPGA implementation example.	olivier.girard	4914d 05h	/openmsp430/trunk/fpga/
79	Update the GPIO peripheral to fix a potential synchronization issue.	olivier.girard	4925d 23h	/openmsp430/trunk/fpga/
74	Update serial debug interface to support memories with a size which is not a power of 2. Update the software tools accordingly.	olivier.girard	5012d 22h	/openmsp430/trunk/fpga/

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[/] [openmsp430/] [trunk/] [fpga/] - Rev 110

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