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[/] [openmsp430/] [trunk/] [fpga/] - Rev 33

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32 Minor update to the HTML documentation + add some SVN ignore properties to the Altera FPGA project simulation directory. olivier.girard 5267d 06h /openmsp430/trunk/fpga/
30 Add Altera Cyclone II FPGA project example (thanks to Vadim Akimov contribution). olivier.girard 5267d 07h /openmsp430/trunk/fpga/
29 Add Altera Cyclone II FPGA project example. olivier.girard 5267d 08h /openmsp430/trunk/fpga/
28 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5275d 15h /openmsp430/trunk/fpga/
27 renamed "diligent_s3board" directory to "xilinx_diligent_s3board" olivier.girard 5275d 15h /openmsp430/trunk/fpga/
26 Xilinx implementation example:
- update the project directory structure.
- make a local copy of the openMSP430 core to make the project self contained.		 olivier.girard 5275d 15h /openmsp430/trunk/fpga/
25 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5365d 13h /openmsp430/trunk/fpga/
24 FPGA Setup: Created some BAT files for WINDOWS users. olivier.girard 5365d 13h /openmsp430/trunk/fpga/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5386d 11h /openmsp430/trunk/fpga/
20 added some SVN ignore patterns.
small update to html documentation		 olivier.girard 5412d 05h /openmsp430/trunk/fpga/
16 Updated header with SVN info olivier.girard 5412d 07h /openmsp430/trunk/fpga/
5 Added some ignore pattern properties... olivier.girard 5434d 08h /openmsp430/trunk/fpga/
3 update FPGA inc file to match the CORE version olivier.girard 5446d 18h /openmsp430/trunk/fpga/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5447d 06h /openmsp430/trunk/fpga/

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