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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_clock_module.v] - Rev 205

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205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3230d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
202 Add DMA interface support + LINT cleanup olivier.girard 3244d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
181 Update with latest oMSP Core version. olivier.girard 4100d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
136 Update all FPGA projects with the latest core version. olivier.girard 4440d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4747d 13h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
107 Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version. olivier.girard 4803d 11h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4822d 14h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
85 Diverse RTL cosmetic updates. olivier.girard 4859d 12h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4913d 20h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_clock_module.v

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