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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] [verilog/] [openmsp430/] [omsp_execution_unit.v] - Rev 202

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202 Add DMA interface support + LINT cleanup olivier.girard 3232d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
190 Remove dummy memory read access for CMP and BIT instructions. olivier.girard 3933d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4114d 02h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
136 Update all FPGA projects with the latest core version. olivier.girard 4428d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4525d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4735d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4806d 03h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4810d 04h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v
80 Create initial version of the Actel FPGA implementation example. olivier.girard 4901d 10h /openmsp430/trunk/fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_execution_unit.v

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