URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [omsp_multiplier.v] - Rev 111

Rev	Log message	Author	Age	Path
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4738d 09h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4792d 18h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4813d 09h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5177d 09h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_multiplier.v