URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] [openMSP430_undefines.v] - Rev 72

Rev	Log message	Author	Age	Path
72	Expand configurability options of the program and data memory sizes.	olivier.girard	5038d 05h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
71	Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier.	olivier.girard	5185d 04h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
59	Update the FPGA projects with the latest core design updates.	olivier.girard	5219d 01h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
37		olivier.girard	5253d 03h	/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
33	In order to avoid confusion, the following changes have been implemented to the Verilog code: - renamed the "rom_" ports and defines to "pmem_" (program memory). - renamed the "ram_" ports and defines to "dmem_" (data memory). In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.	olivier.girard	5253d 06h	/openmsp430/trunk/core/rtl/verilog/openMSP430_undefines.v