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Rev	Log message	Author	Age	Path
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4794d 11h	/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4809d 12h	/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4813d 13h	/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4814d 19h	/
102	Fixed bug reported by Mihai ( http://opencores.org/bug,view,1955 ). The following PUSH instructions are now working as expected: - indexed mode: PUSH x(R1) - indirect register mode: PUSH @R1 - indirect autoincrement: PUSH @R1+	olivier.girard	4815d 11h	/
101	Cosmetic change in order to prevent an X propagation whenever executing a byte instruction with an uninitialized memory location as source.	olivier.girard	4815d 13h	/
100	Update HTML documentation with Actel's FPGA implementation example (file & directory description section).	olivier.girard	4818d 12h	/
99	Small fix for CVER simulator support.	olivier.girard	4819d 13h	/
98	Added support for VCS verilog simulator. VPD and TRN waveforms can now be generated.	olivier.girard	4819d 13h	/
97	Update Tools' Windows executables with EraseROM command fix.	olivier.girard	4820d 13h	/
96	Fixed EraseROM command in the TCL library of the Software development tools.	olivier.girard	4820d 13h	/
95	Update some test patterns for the additional simulator supports.	olivier.girard	4823d 13h	/
94	Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators: - Icarus Verilog - Cver - Verilog-XL - NCVerilog - Modelsim	olivier.girard	4823d 13h	/
93	Update Tools' Windows executables.	olivier.girard	4827d 12h	/
92	Fixed bug where the openmsp430-minidebug application shows data memory size instead of program memory size and program memory size instead of data memory size. Thanks to "dir" for reporting the bug :-)	olivier.girard	4827d 14h	/
91	Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface. This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.	olivier.girard	4827d 14h	/
90	Update windows executables for the tools.	olivier.girard	4842d 19h	/
89	Update the loader tool to support Intel-HEX format.	olivier.girard	4842d 19h	/
88	Update windows executables for the tools.	olivier.girard	4842d 20h	/
87	Minor update of gdbproxy to allow sourcing some custom tcl scripts. Major update of the minidebugger (complete re-work of the GUI).	olivier.girard	4842d 20h	/

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[/] - Rev 106

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