URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] - Rev 122

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
122	Add coverage report generation (NCVERILOG only) Add support for the ISIM Xilinx simulator.	olivier.girard	4603d 04h	/
121	Add a new FPGA example for the LX9 Microboard from Avnet. Many thanks to Ricardo Ribalda Delgado for his contribution on this one :-)	olivier.girard	4675d 04h	/
120	update tools changelog...	olivier.girard	4706d 11h	/
119	Slight improvement of the gdbproxy to improve the support of the EMBSYSREGVIEW Eclipse plugin.	olivier.girard	4706d 12h	/
118	Changelog update (move to modified BSD license).	olivier.girard	4707d 05h	/
117	To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license.	olivier.girard	4707d 05h	/
116	Update documentation to reflect the latest core updates.	olivier.girard	4723d 05h	/
115	Add linker script example.	olivier.girard	4732d 05h	/
114	Improved the VerifyCPU_ID procedure.	olivier.girard	4735d 04h	/
113	Created ChangeLog files...	olivier.girard	4736d 04h	/
112	Modified comment.	olivier.girard	4740d 04h	/
111	Re-organized the "openMSP430_defines.v" file. Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning). Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000). As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.	olivier.girard	4741d 04h	/
110	Rework of the GUI for the software development tools. Added possibility to give custom information through the omsp_alias.xml file.	olivier.girard	4742d 04h	/
109	Update Xilinx FPGA example with the latest openMSP430 core RTL version.	olivier.girard	4795d 13h	/
108	Add serial debug interface tasks to the Actel fpga simulation environment.	olivier.girard	4797d 02h	/
107	Update Actel and Alter FPGA examples with the latest openMSP430 core RTL version.	olivier.girard	4797d 02h	/
106	Separated the Timer A defines from the openMSP430 ones. Added the "dbg_en" port in order to allow a separate reset of the debug interface. Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped). Renamed "per_wen" to "per_we" to prevent confusion with active low signals. Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).	olivier.girard	4797d 02h	/
105	Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions. These were not problematic but this is simply cleaner that way.	olivier.girard	4812d 03h	/
104	Update all FPGA example projects with the latest RTL version.	olivier.girard	4816d 04h	/
103	Removed the timescale from all RTL files. Added possibility to exclude the "includes" statements from the RTL.	olivier.girard	4817d 10h	/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories openmsp430

[/] - Rev 122

Filtering Options