URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 136

Rev	Log message	Author	Age	Path
116	Updated to fix l.maci and add tests for l.mac, l.maci, l.macrc and l.msb. Fixed bugs in the old Or1ksim mul test at the same time.	jeremybennett	5104d 03h	/openrisc/
115	Added support for l.fl1 and tests for l.ff1 and l.fl1	jeremybennett	5105d 03h	/openrisc/
114	l.addic added. Tests of l.add, l.addc, l.addi and l.addic completed. All set overflow correctly, triggering a range exception if the OVE bit is set in the SR.	jeremybennett	5105d 04h	/openrisc/
113	Updates to exception handling for l.add and l.div	jeremybennett	5106d 03h	/openrisc/
112	Tidy ups to Ethernet test fixes. new tests for l.add. Fixes so l.add computes overflow correctly, and generates a range exception if the the OVE bit is set in the supervision register.	jeremybennett	5106d 03h	/openrisc/
111	Changed conditionals for Verilator to "verilator" instead of "VERILATOR".	jeremybennett	5106d 07h	/openrisc/
110	or1ksim make check should work without a libc in the or32-elf tools	julius	5107d 04h	/openrisc/
109	or_debug_proxy does signals with signals, just ignores signals	julius	5107d 12h	/openrisc/
108	Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu.	jeremybennett	5109d 02h	/openrisc/
107	New instruction set testing infrastructure. Fix for l.div/li.divu (Bug 1770) and tests for that bug.	jeremybennett	5109d 03h	/openrisc/