URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 390

Rev	Log message	Author	Age	Path
370	Toolchain install script uclibc url fix	julius	5000d 18h	/openrisc/
369	Toolchain build script binutils path fix	julius	5000d 19h	/openrisc/
368	Toolchain script: adding sim url path	julius	5000d 19h	/openrisc/
367	Fixup 1.0 release script	julius	5000d 19h	/openrisc/
366	Version 1.0 toolchain script commit	julius	5000d 19h	/openrisc/
365	Linux-2.6.34 patch update with updated USB ohs900 host	julius	5003d 13h	/openrisc/
364	OR1200 passes verilator lint. Mainly fixes to widths, and all case statements altered to casez and Xs changed to ?s. OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20 last checkin) OR1200 spec updated to version 0.9, various updates. OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.	julius	5012d 12h	/openrisc/
363	ORPSoC's RTL code fixed to pass linting by Verilator. ORPSoC's debug interface disabled for now in both RTL and System C top level. Profiled building of cycle-accurate model now done correctly.	julius	5012d 22h	/openrisc/
362	ORPSoCv2 verilator building working again. Board build fixes to follow	julius	5014d 07h	/openrisc/
361	OPRSoCv2 - adding things left out in last check-in	julius	5014d 12h	/openrisc/