OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 449

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4902d 11h /openrisc/
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4902d 21h /openrisc/
447 Updates to register order. jeremybennett 4903d 15h /openrisc/
446 gdb-7.2 gdbserver updates. julius 4904d 10h /openrisc/
445 gdbserver update to use kernel port ptrace register definitions. julius 4905d 06h /openrisc/
444 Changes to ABI handling of varargs. jeremybennett 4905d 15h /openrisc/
443 Work in progress on more efficient Ethernet. jeremybennett 4905d 19h /openrisc/
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4906d 09h /openrisc/
441 Changes for gdbserver. jeremybennett 4906d 16h /openrisc/
440 Updated documentation to describe new Ethernet usage. jeremybennett 4907d 11h /openrisc/
439 ORPSoC update

Ethernet MAC synthesis issues with Actel Synplify D-2009.12A
Ethernet MAC FIFO synthesis issues with Xilinx XST

Multiply/divide tests for to run on target.

Added third interface to ram_wb module, changed reference design RAM to ram_wb
wrapper. Updated verilog and system C monitor modules accordingly.

Added ability to use ram_wb as internal memory on ML501 design.

Fixed ethernet MAC tests for ML501.
julius 4909d 15h /openrisc/
438 Fix to newlib header and library locations. jeremybennett 4912d 15h /openrisc/
437 Or1ksim - ethernet peripheral update, working much better. julius 4915d 05h /openrisc/
436 Or1ksim ethernet TAP updates. Ethernet test still failing. julius 4916d 05h /openrisc/
435 ORPSoC updates
OR1200 multiply/MAC/division unit update with serial multiply and
divide options. Full divide not synthesizable yet.
New software tests of multiply and divide functionality.
julius 4916d 06h /openrisc/
434 Work in progress with new Ethernet TUN/TAP interface. jeremybennett 4919d 11h /openrisc/
433 New single program interrupt test programs. jeremybennett 4920d 14h /openrisc/
432 Updates to handle interrupts correctly. jeremybennett 4920d 15h /openrisc/
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.
julius 4922d 14h /openrisc/
430 or1ksim - clarifying interrupt behavior in code and documentation. julius 4923d 11h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.