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[/] [openrisc/] - Rev 498

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Rev Log message Author Age Path
498 or_debug_proxy updates to documentation and Makefile related to latest ftd2xx driver, julius 4823d 01h /openrisc/
497 or_debug_proxy updates julius 4823d 21h /openrisc/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4823d 22h /openrisc/
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 4823d 22h /openrisc/
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4834d 16h /openrisc/
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 4837d 00h /openrisc/
492 ORPSoC VPI interface for modelsim and documentation update julius 4837d 22h /openrisc/
491 ORPSoC or1200_monitor update. julius 4838d 09h /openrisc/
490 Updates to fix spurious test failures and register scheduling. jeremybennett 4842d 15h /openrisc/
489 ORPSoC sw cleanup. Remove warnings. julius 4847d 21h /openrisc/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4847d 22h /openrisc/
487 ORPSoC main software makefile update julius 4850d 20h /openrisc/
486 ORPSoC updates, mainly software, i2c driver julius 4850d 20h /openrisc/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4855d 00h /openrisc/
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 4855d 23h /openrisc/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4858d 01h /openrisc/
482 Don't hardcode tool versions in help text olof 4859d 13h /openrisc/
481 OR1200 Update. RTL and spec. julius 4871d 07h /openrisc/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4872d 05h /openrisc/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4873d 04h /openrisc/

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