URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 513

Rev	Log message	Author	Age	Path
493	ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues.	julius	4826d 04h	/openrisc/
492	ORPSoC VPI interface for modelsim and documentation update	julius	4827d 02h	/openrisc/
491	ORPSoC or1200_monitor update.	julius	4827d 13h	/openrisc/
490	Updates to fix spurious test failures and register scheduling.	jeremybennett	4831d 19h	/openrisc/
489	ORPSoC sw cleanup. Remove warnings.	julius	4837d 02h	/openrisc/
488	ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added.	julius	4837d 02h	/openrisc/
487	ORPSoC main software makefile update	julius	4840d 00h	/openrisc/
486	ORPSoC updates, mainly software, i2c driver	julius	4840d 00h	/openrisc/
485	ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501	julius	4844d 05h	/openrisc/
484	Changes to make r12 call-saved and to bring wchar tests in line.	jeremybennett	4845d 03h	/openrisc/