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67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5219d 21h /openrisc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5239d 19h /openrisc/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5244d 01h /openrisc/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5246d 21h /openrisc/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5256d 18h /openrisc/
62 This material is part of the separate website downloads directory. jeremybennett 5267d 21h /openrisc/
61 The build directory should not be part of the SVN configuration. jeremybennett 5267d 21h /openrisc/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5274d 14h /openrisc/
59 Toolchain install script gcc patch change and gdb configure change julius 5295d 15h /openrisc/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5298d 13h /openrisc/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5303d 17h /openrisc/
56 adding generic pll model to orpsoc julius 5311d 20h /openrisc/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5314d 10h /openrisc/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5324d 17h /openrisc/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5342d 18h /openrisc/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5343d 14h /openrisc/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5357d 16h /openrisc/
50 Adding or32_funcs.S julius 5357d 20h /openrisc/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5376d 10h /openrisc/
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5376d 13h /openrisc/

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