OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] - Rev 79

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
79 Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board julius 5156d 23h /openrisc/
78 Fixed typo in Silos workaround script rherveille 5157d 18h /openrisc/
77 Added support for Silvaco's Silos simulator
Added workaround for Silos's exit code behaviour		 rherveille 5157d 18h /openrisc/
76 Added: +libext+.v
Added: +incdir+.		 rherveille 5158d 18h /openrisc/
75 Fixed toolchain script's cygwin ncurses check julius 5163d 20h /openrisc/
74 Toolchain script fix for ncurses header checking julius 5181d 23h /openrisc/
73 toolchain script error fix julius 5182d 00h /openrisc/
72 Toolchain install script: or1ksim location changed, few tweaks julius 5184d 21h /openrisc/
71 ORPSoC board builds, adding readmes julius 5201d 04h /openrisc/
70 ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\! julius 5205d 08h /openrisc/
69 ORPSoC xilinx ml501 board update - added ethernet eupport and software test julius 5205d 09h /openrisc/
68 Fixed up a couple of Makefile things in ORPSoCv2 julius 5208d 01h /openrisc/
67 New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory julius 5208d 04h /openrisc/
66 Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software. julius 5228d 02h /openrisc/
65 ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix julius 5232d 08h /openrisc/
64 Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile. julius 5235d 03h /openrisc/
63 Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores. julius 5245d 00h /openrisc/
62 This material is part of the separate website downloads directory. jeremybennett 5256d 03h /openrisc/
61 The build directory should not be part of the SVN configuration. jeremybennett 5256d 04h /openrisc/
60 Mark Jarvin's patches to support Mac OS X (Snow Leopard). jeremybennett 5262d 21h /openrisc/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.