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353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 4998d 03h /openrisc/trunk/
352 OR1200 RTL DC sensitivity list fix julius 4999d 00h /openrisc/trunk/
351 OR1200 with icarus fixed up. MMu test fix, remove testfloat elf, adding new arbiter and RAM, may break verilator compatibility... TODO julius 4999d 00h /openrisc/trunk/
350 Adding new OR1200 processor to ORPSoCv2 julius 4999d 04h /openrisc/trunk/
349 ORPSoCv2 update with new software and makefile update julius 4999d 04h /openrisc/trunk/
348 First stage of ORPSoCv2 update - more to come julius 4999d 05h /openrisc/trunk/
346 Changes to support Or1ksim 0.5.0rc1

Top level changes:

* config.h.in: Regenerated.
* debug.cfg, rsp.cfg: Deleted.
* doc/or1ksim.texi: Updated for new options and library interface.
* doc/or1ksim.info, doc/version.texi: Regenerated.
* Makefile.am: Added sim.cfg to EXTRA_DIST.
* NEWS: Updated for 0.5.0rc1.
* or1ksim.h <enum or1ksim_rc>: OR1KSIM_RC_OK explicitly zero.
* sim.cfg: Updated for consistency with the user guide.
* sim-config.c (init_defconfig): 50000 as default VAPI port.
(alloc_memory_block): Verbose message of amount allocated.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.

Changes in testsuite:

* libsim.tests/int-edge.exp <int-edge simple 1>: Increase time
between interrupts to 2ms.
<int-edge simple 2>: Increase time between interrupts to 2ms.
<int-edge duplicated 1>: Increase time between interrupts to 2ms.
<int-edge duplicated 2>: Increase time between interrupts to 2ms.

Changes in testsuite/test-code-or1k:

* mc-common/except-mc.S: Remove leading underscores from global
symbols.
* except/except.S: Remove leading underscores from global symbols.
* cache/cache-asm.S: Remove leading underscores from global symbols.
* cache/cache.c (jump_and_link): Remove leading underscore from
label.
(jump): Remove leading underscore from label.
(all): Remove leading underscore from global symbol references.
* testfloat/systfloat.S: Remove leading underscores from global
symbols.
* mmu/mmu.c (jump): Remove leading underscore from label.
* mmu/mmu-asm.S: Remove leading underscores from global symbols.
* except-test/except-test.c: Remove leading underscores from
global symbols.
* except-test/except-test-s.S: Remove leading underscores from
global symbols.
* uos/except-or32.S: Remove leading underscores from global
symbols.
* configure: Regenerated.
* configure.ac: Version changed to 0.5.0rc1.		 jeremybennett 4999d 06h /openrisc/trunk/
343 Build C++ and its libraries. jeremybennett 5000d 03h /openrisc/trunk/
342 Various files regenerated as part of RC1 creation. jeremybennett 5000d 03h /openrisc/trunk/
339 Updates for GDB 7.2 for OpenRISC version 1.0 release candidate 1. OpenRISC
documentation subsumes the old separate OpenRISC document.		 jeremybennett 5000d 08h /openrisc/trunk/
336 Corrected for 4.5.1-or32-1.0rc1 jeremybennett 5001d 01h /openrisc/trunk/
335 Updated version number to 4.5.1-or32-1.0. jeremybennett 5001d 01h /openrisc/trunk/
334 Record changes to the documentation and option handling. jeremybennett 5001d 01h /openrisc/trunk/
333 Fix the default option (to use -mhard-mul). Update the documentation for
OpenRISC.		 jeremybennett 5001d 01h /openrisc/trunk/
332 Provide support for nested functions. Tidy up board specification.

* config/or32/or32-protos.c <or32_trampoline_code_size>: Added.
* config/or32/or32.c <OR32_MOVHI, OR32_ORI, OR32_LWZ, OR32_JR>:
New macros added.
(or32_emit_mode, or32_emit_binary, or32_force_binary)
(or32_trampoline_code_size, or32_trampoline_init): Created.
(or32_output_bf): Tabbing fixed.
<TARGET_TRAMPOLINE_INIT>: Definition added.
* config/or32/or32.h <STATIC_CHAIN_REGNUM>: Uses R11.
<TRAMPOLINE_SIZE>: redefined.
<TRAMPOLINE_ENVIRONMENT>: Added definition.		 jeremybennett 5002d 01h /openrisc/trunk/
331 Updated for GDB 7.2 and GCC 4.5.1 (which needs target-libgcc). jeremybennett 5002d 09h /openrisc/trunk/
330 Baseline port of GDB 7.2 for OpenRISC 1000 jeremybennett 5002d 19h /openrisc/trunk/
329 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5002d 20h /openrisc/trunk/
328 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5002d 20h /openrisc/trunk/
327 Baseline GCC 4.5.1 port for the OpenRISC 1000 jeremybennett 5002d 20h /openrisc/trunk/

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