OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 498

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
498 or_debug_proxy updates to documentation and Makefile related to latest ftd2xx driver, julius 4823d 15h /openrisc/trunk/
497 or_debug_proxy updates julius 4824d 12h /openrisc/trunk/
496 ORPSoC ml501 updates - increased frequency, updated documentation julius 4824d 13h /openrisc/trunk/
495 ORPSoC adding more accessor functions to Micron SDRAM model. julius 4824d 13h /openrisc/trunk/
494 Change to ensure handles ctrl-C correctly with empty line. jeremybennett 4835d 07h /openrisc/trunk/
493 ORPSoC VPI JTAG interface, hopefully fix 64-bit machine compile issues. julius 4837d 15h /openrisc/trunk/
492 ORPSoC VPI interface for modelsim and documentation update julius 4838d 13h /openrisc/trunk/
491 ORPSoC or1200_monitor update. julius 4839d 00h /openrisc/trunk/
490 Updates to fix spurious test failures and register scheduling. jeremybennett 4843d 06h /openrisc/trunk/
489 ORPSoC sw cleanup. Remove warnings. julius 4848d 12h /openrisc/trunk/
488 ORPSoC OR1200 driver - tick timer exception handler reverted to generic - cpu tick function hook used as default in handler table. OR1200 timer demo sw for board added. julius 4848d 13h /openrisc/trunk/
487 ORPSoC main software makefile update julius 4851d 11h /openrisc/trunk/
486 ORPSoC updates, mainly software, i2c driver julius 4851d 11h /openrisc/trunk/
485 ORPSoC updates - or1200 monitor now has separate defines file, ethmac updates to fifos and wishbone IF, board.h changes for UART (may propegate to other drivers with multiple cores, we'll see), crt0.S for or1200 now zeros all registers on reset, adding own ethernet tests for ML501 julius 4855d 15h /openrisc/trunk/
484 Changes to make r12 call-saved and to bring wchar tests in line. jeremybennett 4856d 14h /openrisc/trunk/
483 Updated with new opcodes to generate random numbers and to identify us as Or1ksim. jeremybennett 4858d 16h /openrisc/trunk/
482 Don't hardcode tool versions in help text olof 4860d 04h /openrisc/trunk/
481 OR1200 Update. RTL and spec. julius 4871d 22h /openrisc/trunk/
480 ORPSoC updates - ml501 project cleanups, DDR2 cache bug fixes. julius 4872d 20h /openrisc/trunk/
479 ORPSoC update to ml501 board port. Memory controller caching fixed up, does multiple lines of cache and Wishbone bursting. julius 4873d 19h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.