OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 59

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
59 Toolchain install script gcc patch change and gdb configure change julius 5272d 12h /openrisc/trunk/
58 ORPSoC2 update - added fpu and implemented in processor, also some sw tests for it, makefile for event sims cleaned up julius 5275d 10h /openrisc/trunk/
57 ORPSoC execution logs created by event sim and cycle accurate should now be equivalent. Changed some of the rule names in orpsoc main makefile to make all rules use hyphens instead of underscores between words julius 5280d 14h /openrisc/trunk/
56 adding generic pll model to orpsoc julius 5288d 16h /openrisc/trunk/
55 Added modelsim support to makefile. Moved buffer libraries to sensible place. Removed a lot of junk julius 5291d 07h /openrisc/trunk/
54 wb_conbus wishbone arbiter now in orpsocv2 instead of synthesized netlist julius 5301d 14h /openrisc/trunk/
53 Fixed incorrect commandline option for ORPSoC and main makefile setting julius 5319d 15h /openrisc/trunk/
52 ORPSoC update - ability to dump part or all of SRAM contents at the end of simulation julius 5320d 11h /openrisc/trunk/
51 ORPSoCv2 updates: cycle accurate profiling, ELF loading julius 5334d 13h /openrisc/trunk/
50 Adding or32_funcs.S julius 5334d 17h /openrisc/trunk/
49 Lots of ORPSoC Updates. Cycle accurate model update. Enabled block read from CPU via debug interface. SMII interface same as devboard but may be broken in sim now. Makefile update julius 5353d 07h /openrisc/trunk/
48 Adds an initialization to keep GCC happy in jp1_ll_read_jp1. jeremybennett 5353d 10h /openrisc/trunk/
47 debug proxy speed increase, block transfers possible with cpu aslong as dbg_interface has appropriate change, usb chip reinit function, changed some of the retry code in the usb transfer functions julius 5362d 17h /openrisc/trunk/
46 debug interfaces now support byte and non-aligned accesses from gdb julius 5368d 18h /openrisc/trunk/
45 Orpsoc eth test fix and script error message update julius 5375d 18h /openrisc/trunk/
44 New SystemC model monitoring functions, ethernet PHY model and test sw, smii decoder for ethernet PHY, various makefile upgrades julius 5404d 17h /openrisc/trunk/
43 Couple of fixes to ORPSoC, new linux patch version in toolchain script julius 5428d 14h /openrisc/trunk/
42 Fixed ORPSoCv2 VCD dumping and UART output in cycleaccurate model julius 5444d 11h /openrisc/trunk/
41 Update to or1k top julius 5447d 13h /openrisc/trunk/
40 Added GDB server to verilog simulation via VPI and make target to build and run this model julius 5448d 18h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.