OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 791

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
791 Added options to configure RAM and ROM sizes. Fixed cache handling. skrzyp 4426d 15h /openrisc/trunk/
790 fixed issues with context switching, interrupts, optimizations and cleanups skrzyp 4433d 16h /openrisc/trunk/
789 ORPSoC: Patch from R Diez to make RTL sim report l.nops have equivalent formatting to those from or1ksim

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4437d 11h /openrisc/trunk/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>
julius 4437d 12h /openrisc/trunk/
787 Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:

2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
* except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
* inst-set-test/inst-set-test.S, int-test/int-test.S,
* mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
start-up. There is no guarantee that R0 is hardwired to zero, and
indeed it is not when simulating the or1200 Verilog core.
* configure: Regenerated.
* configure.ac: Updated version.
jeremybennett 4438d 20h /openrisc/trunk/
786 new ecos tree (tracking mainline) skrzyp 4438d 20h /openrisc/trunk/
785 We are about to upload a new tree (that has a different structure) skrzyp 4438d 21h /openrisc/trunk/
784 Patch from R Diez to ensure DejaGnu handles errors better. Autoconf infrastructure all updated.

2012-03-21 Jeremy Bennett <jeremy.bennett@embecosm.com>

Patch from R Diez <rdiezmail-openrisc@yahoo.de>

* Makefile.am: Add AM_RUNTESTFLAGS to trigger correct error
behaviour.
jeremybennett 4440d 11h /openrisc/trunk/
781 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4456d 21h /openrisc/trunk/
780 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
779 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
778 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
777 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
776 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
775 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
774 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
773 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
772 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
771 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/
770 Initial check-in of GCC, with properties matching the upstream. jeremybennett 4459d 11h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.