OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 816

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
816 Restructuring to put all except the current stable version in a separate directory. jeremybennett 4231d 04h /openrisc/trunk/
815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.		 yannv 4241d 08h /openrisc/trunk/
814 orpsoc/or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4256d 01h /openrisc/trunk/
813 or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4256d 01h /openrisc/trunk/
812 Fix for Bug 86 - Problem with or1k_interrupt_handler_add() stekern 4320d 08h /openrisc/trunk/
811 added exec command to redboot skrzyp 4359d 06h /openrisc/trunk/
810 Added SPI driver skrzyp 4361d 06h /openrisc/trunk/
809 OR1200: Regenerate documentation.

Forgot newline in version history table, so last entry was missing.		 julius 4371d 18h /openrisc/trunk/
808 OR1200: Add DSX bit support to SR.

Updated documentation, revision is now 13.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85		 julius 4371d 18h /openrisc/trunk/
807 ORPSoC: Commit for bug 85 - add DSX support to OR1200.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85

Also added software tests, and added these tests to default regression test list		 julius 4371d 18h /openrisc/trunk/
806 OR1200: Fix for bug 90

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90		 julius 4371d 19h /openrisc/trunk/
805 ORPSoC: Fix for bug 90 - EPCR on range exception bug

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90		 julius 4371d 19h /openrisc/trunk/
804 OR1200: Fix for bug 91

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91		 julius 4371d 19h /openrisc/trunk/
803 ORPSoC: Fix for bug 91, l.sub not setting overflow flag correctly

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91		 julius 4371d 19h /openrisc/trunk/
802 OR1200: Fix for bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88		 julius 4377d 00h /openrisc/trunk/
801 ORPSoC: Fix bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88		 julius 4377d 00h /openrisc/trunk/
800 FreeRTOSV6.1.1
add or32_dma demo task for test dcache manuplation function
add simple driver of wb_dma		 filepang 4389d 15h /openrisc/trunk/
799 FreeRTOSV6.1.1
add cache related function from u-boot from OpenRISC
enable I/D cache if present		 filepang 4390d 16h /openrisc/trunk/
798 Added drivers for ethmac and sdcard_mass_storage_controller skrzyp 4393d 01h /openrisc/trunk/
797 testsuite: kill test processes that timeout pgavin 4401d 06h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.