OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] - Rev 855

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
855 Publish OR1K 1.0 architecture spec julius 4153d 10h /openrisc/trunk/
854 Add OR1200_OR32_LWS define to board specific or1200_defines.v stekern 4163d 04h /openrisc/trunk/
853 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4188d 13h /openrisc/trunk/
852 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4188d 13h /openrisc/trunk/
851 changed branch delay flags skrzyp 4191d 13h /openrisc/trunk/
850 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4203d 05h /openrisc/trunk/
849 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4203d 05h /openrisc/trunk/
848 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4203d 05h /openrisc/trunk/
847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4203d 05h /openrisc/trunk/
846 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4203d 05h /openrisc/trunk/
845 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4203d 05h /openrisc/trunk/
844 skrzyp 4203d 22h /openrisc/trunk/
843 Applied RDiez suggestions skrzyp 4203d 22h /openrisc/trunk/
842 Moving GDB 7.1 into the old collection. jeremybennett 4205d 20h /openrisc/trunk/
841 GDB 7.2 is now considered the stable version. jeremybennett 4205d 21h /openrisc/trunk/
840 Relocate GDB 6.8 to the old directory. jeremybennett 4205d 21h /openrisc/trunk/
839 Forgot about updating linker flags, thanks RDiez! skrzyp 4207d 00h /openrisc/trunk/
838 added branch-delay option and sets r0 to zero skrzyp 4207d 13h /openrisc/trunk/
837 Instructions redirecting users to new directories. jeremybennett 4213d 18h /openrisc/trunk/
836 The old legacy directory, which just a README these days. jeremybennett 4213d 19h /openrisc/trunk/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.