OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] - Rev 855

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
852 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4188d 11h /openrisc/trunk/or1200/
847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4203d 02h /openrisc/trunk/or1200/
846 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4203d 02h /openrisc/trunk/or1200/
845 or1200: l.lws support

Using the l.lws instruction doesn't work currently.
It simply skips the instruction. No exception or reaction.
The patch attached simply duplicates the behaviour of
l.lwz for l.lws.

Patch by: Jeppe Græsdal Johansen <jjohan07@student.aau.dk>		 stekern 4203d 02h /openrisc/trunk/or1200/
815 OR1200 debug unit: prevent deadlock when trap instruction stalls

As per mailing list post <20120925160925.5725e06f@latmask.vernier.se>,
the debug unit could deadlock with the instruction decoder if the trap
instruction is held back by a pipeline stall. This change prevents that.

The problem can be reproduced by placing a breakpoint at an unfavorable
position with instruction cache enabled. In our test, this occurred
with or1200-cbasic when placing a breakpoint at test_bss using gdb, but
this is dependent on such factors as cache parameters and compilation
result.		 yannv 4223d 20h /openrisc/trunk/or1200/
813 or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4238d 13h /openrisc/trunk/or1200/
809 OR1200: Regenerate documentation.

Forgot newline in version history table, so last entry was missing.		 julius 4354d 06h /openrisc/trunk/or1200/
808 OR1200: Add DSX bit support to SR.

Updated documentation, revision is now 13.

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=85		 julius 4354d 06h /openrisc/trunk/or1200/
806 OR1200: Fix for bug 90

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=90		 julius 4354d 07h /openrisc/trunk/or1200/
804 OR1200: Fix for bug 91

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=91		 julius 4354d 07h /openrisc/trunk/or1200/
802 OR1200: Fix for bug 88

http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=88		 julius 4359d 12h /openrisc/trunk/or1200/
794 ORPSoC, or1200: split out or1200_fpu_intfloat_conv_except module into own file

Fixes lint warnings.		 julius 4392d 22h /openrisc/trunk/or1200/
788 or1200: Patch from R Diez to remove l.cust5 signal from a sensitivty list when it's not defined.

Signed-off-by: R Diez <rdiezmail-openrisc@yahoo.de>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 julius 4417d 12h /openrisc/trunk/or1200/
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4441d 12h /openrisc/trunk/or1200/
674 or1200: Fix for Bug 76 - Incorrect unsigned integer less-than compare with COMP3 option enabled julius 4483d 20h /openrisc/trunk/or1200/
647 or1200: update documentation to go with recent rtl commits julius 4604d 11h /openrisc/trunk/or1200/
645 or1200: Specification document source now in asciidoc format. ODT and MS Word format documents deprecated, PDF regenerated julius 4622d 10h /openrisc/trunk/or1200/
644 or1200: the infamous l.rfe fix, and bug fix for when multiply is disabled julius 4622d 11h /openrisc/trunk/or1200/
643 or1200: new ALU comparision implementation option, TLB invalidate register indicated as not present, multiply overflow detection bug fix julius 4622d 11h /openrisc/trunk/or1200/
642 or1200: add carry, overflow bits, and range exception julius 4622d 11h /openrisc/trunk/or1200/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.