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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_fsm.v] - Rev 868

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846 or1200: Fix for cache bug related to first_{hit|miss}_ack

Under certain circumstances, when first_hit_ack and
first_miss_ack is asserted at the same time, cache data
would wrongly be overwritten with bus data.

Patch by: Matthew Hicks <firefalcon@gmail.com>		 stekern 4231d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
481 OR1200 Update. RTL and spec. julius 4876d 11h /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 5004d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 5007d 05h /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5017d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
141 added OpenRISC version rel3 marcus.erlandsson 5079d 02h /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
10 or1200 added from or1k subversion repository unneback 5480d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_dc_fsm.v

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