URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dc_top.v] - Rev 481

Rev	Log message	Author	Age	Path
481	OR1200 Update. RTL and spec.	julius	4847d 17h	/openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v
352	OR1200 RTL DC sensitivity list fix	julius	4981d 02h	/openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	4988d 20h	/openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v
141	added OpenRISC version rel3	marcus.erlandsson	5050d 08h	/openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v
10	or1200 added from or1k subversion repository	unneback	5451d 12h	/openrisc/trunk/or1200/rtl/verilog/or1200_dc_top.v