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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_genpc.v] - Rev 859

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859 Execute trapped instruction after breakpoint is removed

Closes bug #104

When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.

Proposed solution:

- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).

- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).

Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org>		 olof 3976d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
852 Declare pcreg_boot before usage

When things were moved around in rev 813, this error was introduced

Signed-off-by: Olof Kindgren <olof at opencores.org>
acked-by: Julius Baxter <julius at opencores.org>		 olof 4208d 01h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
847 or1200_genpc: fix ipcu_cycstb_o generation

In some circumstances the CPU is still waiting for the lsu to finish
while in a pre branch state. However, ipcu_cycstb_o is set and the cycle
starts with the wrong address on the iwb bus (the one before the
branched address).

This fixes this issue.

Patch by: Franck Jullien <franck.jullien@gmail.com>		 stekern 4222d 16h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
813 or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4258d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 4996d 02h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 4998d 11h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 5008d 20h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
186 OR1200 RTL FPU fix - RF writeback signal working properly again julius 5059d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
141 added OpenRISC version rel3 marcus.erlandsson 5070d 08h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v
10 or1200 added from or1k subversion repository unneback 5471d 12h /openrisc/trunk/or1200/rtl/verilog/or1200_genpc.v

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