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[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Rev 364

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364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 4982d 00h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
358 OR1200's reset now configurable as active high or active low. Thanks to patch
from OpenCores contributor Kuoping.

Updated OR1200 in ORPSoCv2 and OR1200 project.		 julius 4984d 09h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
356 Added new simple MAC test to ORPSoC test suite:
* orpsocv2/sw/or1200asm/or1200asm-mac.S: Added

Fixed MAC pipeline issue in OR1200
* or1200/rtl/verilog/or1200_mult_mac.v: Made mac_op valid only once per insn.
* orpsocv2/rtl/verilog/components/or1200/or1200_mult_mac.v: ""

* orpsocv2/sw/dhry/dhry.c: Changed final output to be same as ORPmon version
* orpsocv2/sim/bin/Makefile: Added new MAC test to default tests		 julius 4984d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 4994d 18h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
141 added OpenRISC version rel3 marcus.erlandsson 5056d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v
10 or1200 added from or1k subversion repository unneback 5457d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_mult_mac.v

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