URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32_bw.v] - Rev 679

Rev	Log message	Author	Age	Path
358	OR1200's reset now configurable as active high or active low. Thanks to patch from OpenCores contributor Kuoping. Updated OR1200 in ORPSoCv2 and OR1200 project.	julius	4998d 11h	/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
258	Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off	julius	5008d 21h	/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
142	added OpenRISC version rel3	marcus.erlandsson	5070d 09h	/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
10	or1200 added from or1k subversion repository	unneback	5471d 12h	/openrisc/trunk/or1200/rtl/verilog/or1200_spram_2048x32_bw.v