OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Rev 859

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
859 Execute trapped instruction after breakpoint is removed

Closes bug #104

When the instruction replaced by a trap instruction is restored by the
debugger, this instruction is not executed.

Proposed solution:

- Checked for a debug unstall condition plus a trap condition in
or1200_du(dbg_stall && |except_stop).

- Then, when this event occur, flush the entire pipeline (in or1200_ctrl) and
set the pc to npc in or1200_genpc(which is equal to the trapped instruction
address).

Signed-off-by: Franck Jullien <crevars at opencores.org>
acked-by: Olof Kindgren <olof at opencores.org>		 olof 3964d 02h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
813 or1200: Set correct PC after reset when parameter boot_adr is used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4246d 05h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
679 Allow setting the boot address as an external
parameter. If no parameter is used, the value
from OR1200_BOOT_ADR will be used

Signed-off-by: Olof Kindgren <olof@opencores.org>
Acked-by: Julius Baxter <juliusbaxter@gmail.com>		 olof 4449d 03h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
481 OR1200 Update. RTL and spec. julius 4855d 19h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
364 OR1200 passes verilator lint. Mainly fixes to widths, and all case statements
altered to casez and Xs changed to ?s.

OR1200 PIC default width back to 31 (was accidentally changed to ORPSoC's 20
last checkin)

OR1200 spec updated to version 0.9, various updates.

OR1200 in ORPSoC and main OR1200 in sync, only difference is defines.		 julius 4984d 04h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
258 Big OR1200 update - FPU, data cache write-back added, spec updated, ODT format doc now main one, default config set to both caches 8K, all integer arithmetic, FPU off julius 4996d 22h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
185 Adding single precision FPU to or1200, initial checkin, not fully tested yet julius 5047d 06h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
142 added OpenRISC version rel3 marcus.erlandsson 5058d 10h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v
10 or1200 added from or1k subversion repository unneback 5459d 14h /openrisc/trunk/or1200/rtl/verilog/or1200_top.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.